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Deliverable D5.6.1 - FPGA Prototype of Experimental Component for uGateway |
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Deliverable D5.6.1, FPGA Prototype of Experimental Component for uGateway, a description of the hardware demonstrator and its interfaces. An active interface for a brushless DC motor (BLDC) is shown as an example application. | |||||
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Author: Jürgen Jagst (ARM) |
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Version: Final | |||
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